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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16706-1E
32-bit Microcontroller
CMOS
FR60 MB91313 Series MB91F313
DESCRIPTION
The FR family* is a line of microcontrollers based on a high-performance 32-bit RISC CPU that contains a variety of built-in I/O resources for embedded control applications which require high-performance, high-speed CPU processing. MB91313 series has multiple communication macro channels, suitable for embedded control applications such as TV control. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURES
1. FR CPU
* 32-bit RISC load/store architecture with a five-stage pipeline * Operating frequency 33 MHz (oscillator frequency: 16.5 MHz; oscillator frequency multiplier: 2 (PLL clock multiplication method)) * 16-bit fixed length instructions (basic instructions) * Instruction execution speed : 1 instruction per cycle * Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions : Instructions suitable for embedded applications * Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language * Register interlock functions : Facilitates assembly-language coding (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB91313 Series
* On-chip multiplier supported at the instruction level - Signed 32-bit multiplication : 5 cycles - Signed 16-bit multiplication : 3 cycles * Interrupt (PC, PS save) : 6 cycles, 16 priority levels * Harvard architecture enabling program access and data access to be executed simultaneously * Instruction prefetch feature implemented using a 4-word queue in the CPU * Instruction compatible with the FR family
2. Simple External Bus Interface
Function as an 8-bit or 16-bit multiplexed bus through programmatic settings Operating frequency : Max 16.5 MHz Multiplexed I/O for 8/16-bit data/address Capable of chip-select signal output for 4 completely independent areas configurable in minimum units of 64 Kbytes * Basic bus cycle : 3 cycles * Automatic wait cycle generation function to be programmed for each area * Unused data/address/control signal pins can serve as general-purpose I/O * * * *
3. Built-in Memory
Flash : 544 Kbytes, RAM : 32 Kbytes
4. DMAC (DMA Controller)
* * * * * 5 channels Two transfer sources : Internal peripheral/software Addressing modes : 20/24-bit address selectable (increment/decrement/fixed) Transfer modes : Burst transfer/step transfer/block transfer Transfer data size : Selectable from 8, 16, or 32 bits
5. Bit Search Module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first "0", "1", or changed bit in a word
6. 16-bit Reload Timer (Including 1 Channel for REALOS)
* 6 channels * Internal clock: Frequency division selectable from 2, 8, and 32 (Continued)
2
MB91313 Series
7. Serial Interface
* 11 channels * Full duplex double buffer * Communication mode : Asynchronous (start-stop synchronization) communication, clock synchronous communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max), high-speed mode (400 kbps Max) * Parity on/off selectable * Baud rate generators for each channel * Extensive error detection functions : Parity, frame, and overrun * External clock can be used as transfer clock * Ch.0 to ch.2 : DMA transfers/each equipped with a pair of 16-byte transmit and receive FIFOs * Ch.8 to ch.10 : 5 V tolerant * Ch.8 : Open drain outputs * I2C bridge function (bridges between channels 0, 1, and 2) * SPI mode
8. Interrupt Controller
* * * * External interrupt lines: Total of 24 lines (INT23 to INT0) Interrupts from internal peripherals Programmable 16 priority levels Capable of using wakeup from STOP mode
9. 10-bit A/D Converter
* * * * 10 channels Successive approximation type : Conversion time : About 7.94 s Conversion mode : Single-shot conversion mode, scan conversion mode Activation sources : Software/external trigger
10. PPG
* * * * * * 4 channels 16-bit down counter, 16-bit data register with cycle setting buffer Internal clock : Frequency division selected from 1, 4, 16, and 64 Support for automatic cycle setting by DMA transfer Function for supporting remote control transmission Open drain outputs
11. PWC
* 1 channel (1 input) * 16-bit up counter * Simple digital lowpass filter
12. Multi-function Timer
* * * * * * 4 channels Lowpass filter eliminating noise below a pre-set clock frequency Capable of pulse width measurement using seven types of clock signals Pin input event count function Interval timer function using seven types of clock signals and external input clock Internal HSYNC counter mode (Continued) 3
MB91313 Series
(Continued)
13. HDMI-CEC/Remote Control Receiver
* 2 channels * HDMI-CEC receiver function (with automatic ACK response function) * Remote control receiver function (built-in 4-byte receive buffer)
14. Other Interval Timers
* Watch timer (32 kHz, counts up to a maximum of 60 seconds) * Watchdog timer
15. I/O Ports
Max 86 ports
16. Other Features
Internal oscillator circuit as a clock source INITX provided as a reset pin Watchdog timer reset and software reset are available Stop and sleep modes supported as low-power consumption modes Gear function * Time-base timer * 5 V tolerant I/O (some pins) * Package LQFP-120, 0.50 mm pitch, 16.0 mm x 16.0 mm * CMOS technology (0.18m) * Power supply voltage 3.3 V 0.3 V, 1.8 V 0.15 V dual power supply * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. * * * * *
4
PIN ASSIGNMENT
VSS VDDI P23/SIN1 P24/SOT1/SDA1 (I2C bridge) P25/SCK1/SCL1 (I2C bridge) P26/SIN2 P27/SOT2/SDA2 (I2C bridge) P30/SCK2/SCL2 (I2C bridge) P31/TOT0 P32/TOT1 P33/TOT2 P34/TIN0 P35/TIN1 P36/TIN2 P37/RIN P40/TMO0/INT16 P41/TMO1/INT17 P42/TMO2/INT18 P43/TMO3/INT19 P44/TMI0/INT20 P45/TMI1/INT21/SIN10 P46/TMI2/INT22/SOT10/SDA10 P47/TMI3/INT23/SCK10/SCL10 P60/TOT3/TRG2 P61/TOT4/TRG3 P62/TOT5/RDY P63/TIN3/CLK P64/TIN4 P65/TIN5 VDDE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(TOP VIEW)
(FPT-120P-M21)
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDDE IBREAK ICLK ICS2 ICS1 ICS0 ICD3 ICD2 ICD1 ICD0 TRSTX PC7/TRG1 PC6/TRG0 PC5/PPGB PC4/PPGA PC3 PC2/SCK9/SCL9 PC1/SOT9/SDA9 PC0/SIN9 PE7/SCK8/SCL8/INT7 PE6/SOT8/SDA8/INT6 PE5/SIN8/INT5 PE4/PPG3/INT4 MD2 MD1 MD0 VDDI X0 X1 VSS
VSS PF0/RCIN0 PF1/RCIN1 PF2 PF3 PF4 PF5 PF6 PF7 VDDE VSS AVSS AVRH AVCC PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 PE0/AN8/INT0 PE1/AN9/PPG0/INT1 PE2/PPG1/INT2/ATRG PE3/PPG2/INT3 VDDE INITX X0A X1A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
VDDE P22/SCK0/SCL0 (I2C bridge) P21/SOT0/SDA0 (I2C bridge) P20/SIN0 P57/WR1X P56/WR0X P55/RDX P54/ASX P53/CS3X/PPG3 P52/CS2X/PPG2 P51/CS1X/PPG1 P50/CS0X/PPG0 P17/AD15 P16/AD14/SCK7/SCL7 P15/AD13/SOT7/SDA7 P14/AD12/SIN7 P13/AD11/SCK6/SCL6 P12/AD10/SOT6/SDA6 P11/AD09/SIN6 P10/AD08/SCK5/SCL5 P07/AD07/SOT5/SDA5/INT15 P06/AD06/SIN5/INT14 P05/AD05/SCK4/SCL4/INT13 P04/AD04/SOT4/SDA4/INT12 P03/AD03/SIN4/INT11 P02/AD02/SCK3/SCL3/INT10 P01/AD01/SOT3/SDA3/INT9 P00/AD00/SIN3/INT8 VDDI VSS
MB91313 Series
5
MB91313 Series
PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name VSS VDDI P23 SIN1 P24 SOT1/SDA1 (I C bridge) P25 SCK1/SCL1 (I2C bridge) P26 SIN2 P27 SOT2/SDA2 (I2C bridge) P30 SCK2/SCL2 (I C bridge) P31 TOT0 P32 TOT1 P33 TOT2 P34 TIN0 P35 TIN1 P36 TIN2 P37 RIN P40 16 TMO0 INT16 B
2 2
I/O circuit type* D L L D L L D D D D D D D GND pin
Description
1.8 V power supply pin General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port Reload timer output pin General-purpose port Reload timer output pin General-purpose port Reload timer output pin General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer General-purpose port PWC input pin General-purpose port Multi-function timer output pin External interrupt request input pin (Continued)
6
MB91313 Series
Pin no.
Pin name P41
I/O circuit type* General-purpose port B
Description
17
TMO1 INT17 P42
Multi-function timer output pin External interrupt request input pin General-purpose port
18
TMO2 INT18 P43
B
Multi-function timer output pin External interrupt request input pin General-purpose port
19
TMO3 INT19 P44
B
Multi-function timer output pin External interrupt request input pin General-purpose port
20
TMI0 INT20 P45 TMI1 INT21 SIN10 P46 TMI2 INT22 SOT10/SDA10 P47 TMI3 INT23 SCK10/SCL10 P60
B
Multi-function timer input pin External interrupt request input pin General-purpose port Multi-function timer input pin External interrupt request input pin Serial data input pin General-purpose port Multi-function timer input pin External interrupt request input pin Serial data output pin/I2C data I/O pin General-purpose port Multi-function timer input pin External interrupt request input pin Serial communication clock I/O pin/I2C clock I/O pin General-purpose port
21
B
22
B
23
B
24
TOT3 TRG2 P61
C
Reload timer output pin PPG trigger input pin General-purpose port
25
TOT4 TRG3 P62
C
Reload timer output pin PPG trigger input pin General-purpose port
26
TOT5 RDY
C
Reload timer output pin External ready input pin (Continued)
7
MB91313 Series
Pin no.
Pin name P63
I/O circuit type* General-purpose port C
Description
27
TIN3 CLK P64 TIN4 P65 TIN5 VDDE VSS PF0 RCIN0 PF1 RCIN1 PF2 PF3 PF4 PF5 PF6 PF7 VDDE VSS AVSS AVRH AVCC PD0 AN0 PD1 AN1 PD2 AN2 PD3 AN3 PD4 AN4 PD5 AN5
Event input pin for reload timer External clock output pin General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer 3.3 V power supply pin GND pin General-purpose port HDMI-CEC/Remote control 0 I/O pin General-purpose port HDMI-CEC/Remote control 1 I/O pin General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port 3.3 V power supply pin GND pin A/D converter GND pin A/D converter reference voltage pin A/D converter power supply pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin (Continued)
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C C D D D D D D D D L L L L L L
8
MB91313 Series
Pin no. 51 52
Pin name PD6 AN6 PD7 AN7 PE0 AN8 INT0 PE1 AN9 PPG0 INT1 PE2 PPG1 INT2 ATRG PE3
I/O circuit type* L L General-purpose port
Description
A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin External interrupt request input pin General-purpose port A/D converter analog input pin PPG output pin External interrupt request input pin General-purpose port PPG output pin External interrupt request input pin A/D converter trigger input pin General-purpose port
53
L
54
L
55
B
56 57 58 59 60 61 62 63 64 65 66 67 68
PPG2 INT3 VDDE INITX X0A X1A VSS X1 X0 VDDI MD0 MD1 MD2 PE4 PPG3 INT4 PE5
B G A A A A F F F B
PPG output pin External interrupt request input pin 3.3 V power supply Initial reset pin Sub clock input pin Sub clock output pin GND pin Main clock output pin Main clock input pin 1.8 V power supply pin Mode pin Mode pin Mode pin General-purpose port PPG output pin External interrupt request input pin General-purpose port
69
SIN8 INT5
B
Serial data input pin External interrupt request input pin (Continued) 9
MB91313 Series
Pin no.
Pin name PE6
I/O circuit type* General-purpose port B
Description
70
SOT8/SDA8 INT6 PE7
Serial data output pin/I2C data I/O pin External interrupt request input pin General-purpose port
71
SCK8/SCL8 INT7 PC0 SIN9 PC1 SOT9/SDA9 PC2 SCK9/SCL9 PC3 PC4 PPGA PC5 PPGB PC6 TRG0 PC7 TRG1 TRSTX ICD0 ICD1 ICD2 ICD3 ICS0 ICS1 ICS2 ICLK IBREAK VDDE VSS VDDI
B
Serial communication clock I/O pin/I2C clock I/O pin External interrupt request input pin General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port General-purpose port PPG output pin General-purpose port PPG output pin General-purpose port PPG trigger input pin General-purpose port PPG trigger input pin Development tool reset pin Development tool data pin Development tool data pin Development tool data pin Development tool data pin Development tool status pin Development tool status pin Development tool status pin Development tool clock pin Development tool break pin 3.3 V power supply pin GND pin 1.8 V power supply pin (Continued)
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
B B B B B B B B G K K K K H H H H I
10
MB91313 Series
Pin no.
Pin name P00
I/O circuit type* General-purpose port O
Description
93
AD00 SIN3 INT8 P01 AD01 SOT3/SDA3 INT9 P02 AD02 SCK3/SCL3 INT10 P03 AD03 SIN4 INT11 P04 AD04 SOT4/SDA4 INT12 P05 AD05 SCK4/SCL4 INT13 P06 AD06 SIN5 INT14 P07 AD07 SOT5/SDA5 INT15 P10
External address/data bus I/O pin Serial data input pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial data output pin/I2C data I/O pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial data input pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial data output pin/I2C data I/O pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial data input pin External interrupt request input pin General-purpose port External address/data bus I/O pin Serial data output pin/I2C data I/O pin External interrupt request input pin General-purpose port
94
O
95
O
96
O
97
O
98
O
99
O
100
O
101
AD08 SCK5/SCL5
O
External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin (Continued)
11
MB91313 Series
Pin no.
Pin name P11
I/O circuit type* General-purpose port O
Description
102
AD09 SIN6 P12
External address/data bus I/O pin Serial data input pin General-purpose port
103
AD10 SOT6/SDA6 P13
O
External address/data bus I/O pin Serial data output pin/I2C data I/O pin General-purpose port
104
AD11 SCK6/SCL6 P14
O
External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin General-purpose port
105
AD12 SIN7 P15
O
External address/data bus I/O pin Serial data input pin General-purpose port
106
AD13 SOT7/SDA7 P16
O
External address/data bus I/O pin Serial data output pin/I2C data I/O pin General-purpose port
107
AD14 SCK7/SCL7 P17 AD15 P50 CS0X PPG0 P51
O
External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin General-purpose port External address/data bus I/O pin General-purpose port External chip select pin PPG output pin General-purpose port
108
O
109
C
110
CS1X PPG1 P52
C
External chip select pin PPG output pin General-purpose port
111
CS2X PPG2 P53
C
External chip select pin PPG output pin General-purpose port
112
CS3X PPG3 P54 ASX
C
External chip select pin PPG output pin General-purpose port External address strobe output pin (Continued)
113
C
12
MB91313 Series
(Continued) Pin no. 114 115 116 117 Pin name P55 RDX P56 WR0X P57 WR1X P20 SIN0 P21 118 SOT0/SDA0 (I2C bridge) P22 119 120 SCK0/SCL0 (I2C bridge) VDDE L L I/O circuit type* C C C D General-purpose port External read strobe output pin General-purpose port External data bus write strobe output pin General-purpose port External data bus write strobe output pin General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin 3.3 V power supply pin Description
* : For the details of the I/O circuit types. Refer to " I/O CIRCUIT TYPE".
13
MB91313 Series
I/O CIRCUIT TYPE
Type
X1, X1A
Circuit type
Remarks Oscillator circuit Internal feedback resistance X0 : 1 M X0A : No
Clock input
A
X0, X0A
Standby control * CMOS level output IOH = 4 mA * CMOS level hysteresis input VIH = 0.7 x VDDE * With standby control * 5 V tolerant
P-ch
Digital output
B
N-ch
Digital output
Digital input Standby control * CMOS level output IOH = 4 mA * CMOS level hysteresis input VIH = 0.8 x VDDE * With standby control * With pull-up control * With pull-up resistor (33 k)
Pull-up control
P-ch P-ch
Digital output C
N-ch
Digital output
Digital input Standby control (Continued)
14
MB91313 Series
Type
Circuit type
Remarks * CMOS level output IOH = 4 mA * CMOS level hysteresis input VIH = 0.8 x VDDE With standby control Without pull-up resistor
P-ch
Digital output
D
N-ch
Digital output
Digital input Standby control * CMOS level input * Without standby control
P-ch
F
N-ch
Digital input * CMOS hysteresis input * With pull-up resistor
P-ch
P-ch
G
N-ch
Digital input CMOS level output
P-ch
Digital output H Digital output
N-ch
(Continued)
15
MB91313 Series
Type
Circuit type
Remarks * CMOS hysteresis input * With pull-down resistor * Without standby control
P-ch
I
N-ch N-ch
Digital input * * * * CMOS level output CMOS level input Without standby control With pull-down resistor
P-ch
Digital output K
N-ch N-ch
Digital output
Digital input * * * * CMOS level output CMOS level hysteresis input With standby control Analog input with switch
P-ch
Digital output
Digital output
N-ch
L
Analog input Control Digital input Standby control (Continued)
16
MB91313 Series
(Continued) Type
Circuit type Pull-up control
P-ch P-ch
Remarks * CMOS level output IOH = 4 mA * CMOS input (external bus interface) CMOS level hysteresis input (port, resource) VIH = 0.8 x VDDE * With standby control * With pull-up control * With pull-up resistor (33 k)
Digital output
Digital output O
N-ch
Port input Resource input External bus input Standby control
17
MB91313 Series
HANDLING DEVICES
* Preventing latch-up Latch-up may occur in a CMOS IC if a voltage higher than VDDE or VDDI, or less than VSS is applied to an input or output pin or if a voltage exceeding the rating is applied between VDDE and VSS, or VDDI and VSS. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. * Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor. * Power supply pins In MB91313 series, devices including multiple of VDDE pins, VDDI pins and VSS pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pin and GND pin must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the VDDE pins, VDDI pins and VSS pins of the MB91313 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between VDDE pins, VDDI pins and VSS pins near this device. * Crystal oscillator circuit Noise in proximity to the X0 and X1 (X0A, X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. * Mode pins (MD0 to MD2) When using mode pins, connect them directly to power supply pin or GND pin. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or GND pin on the printed circuit board as possible and connect them with low impedance. * Operation at power-on Ensure that the INITX pin is reset and the settings are initialized (INIT) immediately after the power is turned on. Maintain the "L" level input to the INITX pin during the stabilization wait time immediately after the power on to ensure the stabilization wait time as required by the oscillator circuit (the stabilization wait time is reset to the minimum value when INIT is asserted using the INITX pin). * Note on oscillator input at power-on At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed.
18
MB91313 Series
* Notes on the turning on/off VDDI pin (1.8 V internal power supply) and VDDE pin (3.3 V external pin power supply) Do not apply only VDDE pin (external power supply) voltage continuously (more than one minute) while the VDDI pin (internal power supply) is disconnected as it will adversely affect the reliability of the LSI. When the VDDE pin (external power supply) returns from the off state to the on state, the circuit may not be able to maintain its internal state, for example, due to power supply noise. Power on Power off VDD pin (internal power supply) VDDE pin (external power supply) Analog Signal Signal Analog VDDE pin (external power supply) VDDI pin (internal power supply)
When the power is turned on, the states of the output pins may remain undefined until the internal power supply becomes stable. * Notes on using an external clock When using the external clock as a general rule you should simultaneously supply X0 (X0A) and X1 (X1A) pins. And also, the clock signal to X0 (X0A) should be supplied a clock signal with the reverse phase to X1 (X1A) pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1 (X1A) pin stops at "H" output in STOP mode). Furthermore, supply a clock to X0 (X0A) pin only if the device is operating in less than 12.5 MHz.
Using an External Clock (Normal Method)
X0, X0A X1, X1A
MB91313 series
Cannot be used in STOP mode (oscillation stop mode).
Using an External Clock (available at 12.5 MHz or less)
X0, X0A X1, X1A
Open
MB91313 series
Note : When operating at a frequency of 10 MHz, the delay between the X0 (X0A) and X1 signals should be less than 15 ns.
19
MB91313 Series
* AVCC pin The MB91313 has a built-in A/D converter. A capacitor of approximately 0.1F must be connected between the AVCC pin and AVSS pin.
AVCC
0.1F MB91313 series
AVSS
* Notes when not using the emulator To operate the evaluation MCU on the user system without connecting the emulator, treat each input pin on the evaluation MCU connected to the emulator interface on the user system as shown below. Note that switching circuits or other measures may be needed on the user system. Emulator Interface Pin Treatment Evaluation MCU Pin Name Pin Connection TRSTX INITX Other Pins * Notes on selecting PLL clocks If the crystal oscillator is disconnected or the clock input stops while the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit within the PLL. However, this operation is not guaranteed. Connect to the reset output circuit on the user system. Connect to the reset output circuit on the user system. Open
20
MB91313 Series
RESTRICTIONS
1) Clock control block When an "L" level is input to the INITX pin, ensure that it is maintained for the duration of the oscillation stabilization wait time. 2) Bit Search Module The bit search data register for 0-detection (BSD0), bit search data register for 1-detection (BSD1), and bit search data register for change point detection (BSDC) can be accessed in word. 3) I/O Ports Ports can only be accessed in byte. 4) Low Power Consumption Mode * To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the timebase counter control register, TBCR) and be sure to use the following sequence :
(LDI#value_of_standby, r0) (LDI#_STCR, R12) STB R0, @R12 LDUB @R12, R0 LDUB @R12, R0 NOP NOP NOP NOP NOP ; value_of_standby is the data to write to STCR ; _STCR is the address of STCR (481H) ; Write to the standby control register (STCR) ; Read STCR for synchronous standby ; Perform an additional dummy read of STCR ; 5 x NOP for timing adjustment
* Do not perform any of the following actions when using the monitor debugger. * Set a breakpoint within the sequence of instructions shown above * Perform step execution of the sequence of instructions shown above
21
MB91313 Series
5) Notes on the PS register Some instructions write to the PS register in advance before executing. When a debugger is being used, execution may break within an interrupt handler routine, or the values of the flags within the PS register may be updated due to exception processing. However, the microcontroller is designed to reprocess correctly after returning from the EIT, and to execute before and after the EIT proceeds according to the specifications. * In any following situation, the previous instructions before a DIV0U or DIV0S instruction may take the processing in (1) to (3). - A user interrupt or NMI is accepted - Step execution is performed - A break occurs due to a data event or by being selected from the emulator menu (1) The D0 and D1 flags are updated in advance. (2) The EIT handling routine (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the DIV0U or DIV0S instruction is executed and the D0/D1 flags are updated back to the same value as in step (1). * If any of the OR CCR, ST ILM, or MOV Ri, PS instructions are executed to enable a user interrupt or NMI interrupt source when that interrupt has occurred, the following operation will be performed. (1) The PS register is updated in advance. (2) The EIT handling routine (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS registers are updated back to the same value as in step (1). 6) Watchdog timer The watchdog timer has a function to monitors the program to check that it delays a reset within a certain period of time, and resets the CPU if the program runs out of control and fails to delay the reset. Once the watchdog timer has been enabled, it keeps running until reset. As an exception, the reset is automatically delayed in conditions where the execution of the CPU program stops. It is possible that the watchdog timer will not be triggered if these conditions arise as a result of the system running out of control. In that case, please reset (INIT) using the external INITX pin. 7) Notes on using the A/D converter Do not supply a voltage higher than the VDDE pin to the AVCC pin. 8) Software reset in synchronous mode When using the software reset in synchronous mode, the following two conditions should be satisfied before setting the SRST bit in STCR (standby control register) to "0". * The interrupt enable flag (I-Flag) is set to interrupts disabled (I-Flag = 0) . * The NMI is not being used.
22
MB91313 Series
BLOCK DIAGRAM
FR CPU CORE
32 32
Flash 544 Kbytes
Bit search module
RAM 32 Kbytes
Bus converter
DMAC 5 channels
32 16 adapter
Simple external bus I/F 8/16-bit multiplexed bus
Clock control
Interrupt controller
UART/SIO/I2C 11 channels
A/D converter 10 channels
HDMI-CEC/ Remote control receiver
2 channel
External interrupt Reload timer 6 channels Multifunction timer 4 channels
Ports
PWC 1 channel
PPG 4 channels
23
MB91313 Series
CPU AND CONTROL UNIT
Internal architecture The FR family of CPUs is a line of high-performance cores providing advanced instructions for embedded applications based on the RISC architecture.
1. Features
* RISC architecture Basic instructions : Execute at one instruction per cycle * 32-bit architecture General purpose registers : 32 bits x 16 * 4 Gbytes of linear memory space * Built-in multiplier 32-bit x 32-bit multiplication : 5 cycles 16-bit x 16-bit multiplication : 3 cycles * Enhanced interrupt servicing High-speed response (6 cycles) Multi-level interrupt support Level mask feature (16 levels) * Enhanced I/O manipulation instructions Memory-to-memory transfer instructions Bit manipulation instructions * Basic instruction word length : 16 bits * Lower-power consumption Sleep mode/stop mode Gear function
24
MB91313 Series
2. Internal architecture
The FR family of CPUs uses a Harvard architecture in which the instruction bus and data bus are separated. A 32-bit 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the CPU and peripheral resources. A Harvard Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller.
FRex CPU D-bus I-bus
32
I address
32
External address Harvard
24
I data D address
32
External data Princeton bus converter
16
Data RAM
D data
32
32-bit 16-bit bus converter
Address Data
32 32
16 R-bus
F-bus
Peripheral resources
Internal I/O
Bus converter
25
MB91313 Series
3. Programming model
32 bits
[Initial Value]
R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H
General purpose registers
R12 R13 R14 R15
Program counter Program status Table base register Return pointer System stack pointer User stack pointer
PC PS TBR RP SSP USP ILM SCR CCR
Multiplication and division register
MDH MDL
26
MB91313 Series
4. Register
* General-purpose registers 32 bits
[Initial Value]
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers are used as the accumulator and memory access pointers in CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. * R13 : Virtual accumulator (AC) * R14 : Frame pointer (FP) * R15 : Stack pointer (SP) The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value). * PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. All undefined bits are reserved bits. Reading these bits always returns 0. Writing to them has no effect.
bit 31 bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
27
MB91313 Series
* CCR (Condition Code Register)
bit 7 bit 6 bit 5 S bit 4 I bit 3 N bit 2 Z bit 1 V bit 0 C
[Initial Value]
--00XXXXB
S I N Z V C
: Stack flag : Interrupt Enable flag : Negative flag : Zero flag : Overflow flag : Carrying flag
* SCR (System Condition Code Register)
bit 10 D1 bit 9 D0 bit 8 T
[Initial Value]
XX0B
D1, D0 : Flag for step division This flag stores interim data during execution of step multiplication. T : Step trace trap flag This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. This function therefore cannot be used within a user program when an emulator is being used. * ILM (Interrupt Level Mask Register)
bit 20 ILM4 bit 19 ILM3 bit 18 ILM2 bit 17 ILM1 bit 16 ILM0
[Initial Value]
01111B
This register stores the value of the interrupt level mask, with the value stored in the ILM used as the interrupt level mask. The register is initialized to "01111B" on reset.
28
MB91313 Series
* PC (Program Counter)
bit 31 bit 0
[Initial Value]
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed. The initial value on reset is undefined. * TBR (Table Base Register)
bit 31 bit 0
[Initial Value]
000FFC00H
The table base register stores the starting address of the vector table used for EIT processing. The initial value on reset is 000FFC00H. * RP (Return Pointer)
bit 31 bit 0
[Initial Value]
XXXXXXXXH
The return pointer stores the address to return from a subroutine. When the CALL instruction is executed, the value of the PC is transferred to the RP register. When the RET instruction is executed, the value of the RP is transferred to the PC register. The initial value on reset is undefined. * SSP (System Stack Pointer)
bit 31 bit 0
[Initial Value]
00000000H
The SSP is the system stack pointer. The SSP functions as R15 when the S flag is "0". The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H.
29
MB91313 Series
* USP (User Stack Pointer)
bit 31 bit 0
[Initial Value]
XXXXXXXXH
The USP is the user stack pointer. The USP functions as R15 when the S flag is "1". The USP can be explicitly specified. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction. * MDH, MDL (Multiplication and Division Registers)
bit 31 MDH MDL bit 0
These registers are used for multiplications and divisions and are each 32 bits long. The initial value after a reset is indeterminate.
30
MB91313 Series
MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU. Direct Addressing Areas The following areas in the address space are used as I/O areas. These areas are called direct addressing areas. The addresses of operands in these areas can be specified directly within some instructions. The direct addressing area varies depending on the size of data to be accessed as follows : Byte data access Word data access : 000H to 0FFH : 000H to 3FFH
Half word data access : 000H to 1FFH
2. Memory Map
Single chip mode
00000000H I/O 00000400H I/O 00010000H 00038000H I/O I/O
Internal ROM external bus mode Direct addressing area Refer to " I/O MAP".
Access prohibited Internal RAM 32 Kbytes Access prohibited
Access prohibited Internal RAM 32 Kbytes Access prohibited External area
00040000H
00050000H 00078000H
Internal Flash 544 Kbytes Access prohibited
00100000H 00200000H 007FFFFFH FFFFFFFFH
Internal Flash 544 Kbytes Access prohibited External area Access prohibited
31
MB91313 Series
I/O MAP
The following table shows the correspondence between the memory space area and each of the peripheral resource registers. [How to read the table] Address Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX Read/Write attribute Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 1) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data. Note : The bit values in the register represent the following initial values : * "1" : Initial value "1" * "0" : Initial value "0" * "X" : Initial value "Undefined" * "-" : No physical register at this location Access is prohibited for data access attributes that are not listed. +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port data register
000000H
32
MB91313 Series
Address 000000H 000004H 000008H 00000CH 000010H to 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H, 00003CH 000040H
Register 0 PDR0 [R/W] XXXXXXXX PDR4 [R/W] XXXXXXXX PDRC [R/W] XXXXXXXX 1 PDR1 [R/W] XXXXXXXX PDR5 [R/W] XXXXXXXX PDRD [R/W] XXXXXXXX 2 PDR2 [R/W] XXXXXXXX PDR6 [R/W] --XXXXXX PDRE [R/W] XXXXXXXX 3 PDR3 [R/W] XXXXXXXX Reserved
Block
Reserved PDRF [R/W] XXXXXXXX
Port data register
Reserved ADCTH[R/W] 00000000 ADCTL[R/W] 00000000 ADCH[R/W] 00000000 00000000 ADAT1[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 ADAT9[R] XXXXXX00 00000000 Reserved EIRR0 [R/W] 00000000 DICR [R/W] -------0 ENIR0 [R/W] 00000000 HRCL [R, R/W] ---11111 ELVR0 [R/W] 00000000 00000000 Reserved TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R, RW] 00000000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R, RW] 00000000 00000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R, RW] 00000000 00000000
Reserved
ADAT0[R] XXXXXX00 00000000 ADAT2[R] XXXXXX00 00000000 ADAT4[R] XXXXXX00 00000000 ADAT6[R] XXXXXX00 00000000 ADAT8[R] XXXXXX00 00000000
10-bit A/D converter
Reserved External interrupt 0 to 7 Delayed/I-unit
000044H 000048H 00004CH 000050H 000054H 000058H 00005CH
TMRLR0 [W] XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] XXXXXXXX XXXXXXXX Reserved TMRLR2 [W] XXXXXXXX XXXXXXXX Reserved
Reload timer 0
Reload timer 1
Reload timer 2
(Continued) 33
MB91313 Series
Address 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 34
Register 0 SCR0 [R, R/W] 0--00000 1 SMR0 [W, R/W] 000-0000 2 SSR0 [R, R/W] 0-000011 BGR01 [R/W] 00000000 FCR01 [R/W] 00-00100 3 ESCR0 [R/W] --000000 BGR00 [R/W] 00000000 FCR00 [R/W] 00000000
Block
RDR0/TRD0 [R/W] -------- 00000000 : RDR0 -------- 11111111 : TRD0 ISMK0 [R/W] 01111110 FBYTE01 [R/W] 00000000 SCR1 [R, R/W] 0--00000 IBSA [R/W] 00000000 FBYTE00 [R/W] 00000000 SMR1 [W, R/W] 000-0000
Serial interface 0 FIFO 0
Reserved SSR1 [R, R/W] 0-000011 BGR11 [R/W] 00000000 FCR11 [R/W] 00-00100 ESCR1 [R/W] --000000 BGR10 [R/W] 00000000 FCR10 [R/W] 00000000
RDR1/TRD1 [R/W] -------- 00000000 : RDR1 -------- 11111111 : TRD1 ISMK1 [R/W] 01111110 FBYTE11 [R/W] 00000000 SCR2 [R, R/W] 0--00000 IBSA1 [R/W] 00000000 FBYTE10 [R/W] 00000000 SMR2 [W, R/W] 000-0000
Serial interface 1 FIFO 1
Reserved SSR2 [R, R/W] 0-000011 BGR21 [R/W] 00000000 FCR21 [R/W] 00-00100 ESCR2 [R/W] --000000 BGR20 [R/W] 00000000 FCR20 [R/W] 00000000
RDR2/TRD2 [R/W] -------- 00000000 : RDR2 -------- 11111111 : TRD2 ISMK2 [R/W] 01111110 FBYTE21 [R/W] 00000000 SCR3 [R, R/W] 0--00000 IBSA2 [R/W] 00000000 FBYTE20 [R/W] 00000000 SMR3 [W, R/W] 000-0000
Serial interface 2
Reserved SSR3 [R, R/W] 0-000011 BGR31 [R/W] 00000000 ESCR3 [R/W] --000000 BGR30 [R/W] 00000000
RDR3/TRD3 [R/W] -------- 00000000 : RDR3 -------- 11111111 : TRD3 ISMK3 [R/W] 01111110 SCR4 [R, R/W] 0--00000 IBSA3 [R/W] 00000000
Serial interface 3
Reserved
Reserved SMR4 [W, R/W] 000-0000 SSR4 [R, R/W] 0-000011 BGR41 [R/W] 00000000 ESCR4 [R/W] --000000 BGR40 [R/W] 00000000
RDR4/TRD4 [R/W] -------- 00000000 : RDR4 -------- 11111111 : TRD4 ISMK4 [R/W] 01111110 IBSA4 [R/W] 00000000
Serial interface 4
Reserved
Reserved (Continued)
MB91313 Series
Address 0000B0H
Register 0 SCR5 [R, R/W] 0--00000 1 SMR5 [W, R/W] 000-0000 2 SSR5 [R, R/W] 0-000011 BGR51 [R/W] 00000000 3 ESCR5 [R/W] --000000 BGR50 [R/W] 00000000
Block
0000B4H
RDR5/TRD5 [R/W] -------- 00000000 : RDR5 -------- 11111111 : TRD5 ISMK5 [R/W] 01111110 EIRR1 [R/W] 00000000 EIRR2 [R/W] 00000000 IBSA5 [R/W] 00000000
Serial interface 5
0000B8H 0000BCH 0000C0H 0000C4H 0000C8H, 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H to 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH
Reserved
Reserved ENIR1 [R/W] 00000000 ENIR2 [R/W] 00000000 Reserved PWCCL[R/W] 0000--00 PWCCH[R/W] 00-00000 Reserved Reserved PWC Reserved Reserved ELVR1 [R/W] 00000000 00000000 ELVR2 [R/W] 00000000 00000000 External interrupt 8 to 15 External interrupt 16 to 23 Reserved
PWCD[R] XXXXXXXX XXXXXXXX PWCC2[R/W] 000----PWCUD[R/W] XXXXXXXX XXXXXXXX Reserved T0LPCR [R/W] -----000 T0CCR [R/W] 0-000000
Reserved T0R [R/W] ---00000
T0TCR [R/W] 00000000
T0DRR [R/W] XXXXXXXX XXXXXXXX T1LPCR [R/W] -----000 T1CCR [R/W] 0-000000
T0CRR [R/W] XXXXXXXX XXXXXXXX T1TCR [R/W] 00000000 T1R [R/W] ---00000
T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000
T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000
Multi-function timer
T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000
T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000
T3DRR [R/W] XXXXXXXX XXXXXXXX
T3CRR [R/W] XXXXXXXX XXXXXXXX (Continued) 35
MB91313 Series
Address 000110H 000114H to 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H, 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H to 00017CH
Register 0 1 2 Reserved 3 TMODE [R/W] 00000000 00000000 Reserved PDUT0[W] XXXXXXXX XXXXXXXX PTMR0[R] 11111111 11111111 PDUT1[W] XXXXXXXX XXXXXXXX PTMR1[R] 11111111 11111111 PDUT2[W] XXXXXXXX XXXXXXXX PTMR2[R] 11111111 11111111 PDUT3[W] XXXXXXXX XXXXXXXX PTMR3[R] 11111111 11111111 PCSR0[W] XXXXXXXX XXXXXXXX PCNH0[R/W] 0000000PCNL0[R/W] 000000-0
Block Multi-function timer
Reserved
PPG0
PCSR1[W] XXXXXXXX XXXXXXXX PCNH1[R/W] 0000000PCNL1[R/W] 000000-0
PPG1
PCSR2[W] XXXXXXXX XXXXXXXX PCNH2[R/W] 0000000PCNL2[R/W] 000000-0
PPG2
PCSR3[W] XXXXXXXX XXXXXXXX PCNH3[R/W] 0000000Reserved PCNL3[R/W] 000000-0
PPG3
Reserved TMR3 [R] XXXXXXXX XXXXXXXX TMCSR3 [R, RW] 00000000 00000000 TMR4 [R] XXXXXXXX XXXXXXXX TMCSR4 [R, RW] 00000000 00000000 TMR5 [R] XXXXXXXX XXXXXXXX TMCSR5 [R, RW] 00000000 00000000
TMRLR3 [W] XXXXXXXX XXXXXXXX Reserved TMRLR4 [W] XXXXXXXX XXXXXXXX Reserved TMRLR5 [W] XXXXXXXX XXXXXXXX Reserved
Reload timer 3
Reload timer 4
Reload timer 5
Reserved
Reserved (Continued)
36
MB91313 Series
Address 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH 0001A0H to 0001ACH 0001B0H
Register 0 RCCR0 [R/W] 0---0000 RCDBHW0 [R/W] 00000000 RCDT0HH [R] 00000000 1 RCST0 [R/W] 00000000 Reserved RCDT0HL [R] 00000000 2 RCSHW0 [R/W] 00000000 RCADR01 [R/W] 00000000 RCDT0LH [R] 00000000 3 RCDAHW0 [R/W] 00000000 RCADR02 [R/W] 00000000 RCDT0LL [R] 00000000
Block
Remote controller 0
RCCKD0 [R/W] 00000000 00000000 RCCR1 [R/W] 0---0000 RCDBHW1 [R/W] 00000000 RCDT1HH [R] 00000000 RCST1 [R/W] 00000000 Reserved RCDT1HL [R] 00000000
Reserved RCSHW1 [R/W] 00000000 RCADR11 [R/W] 00000000 RCDT1LH [R] 00000000 RCDAHW1 [R/W] 00000000 RCADR12 [R/W] 00000000 RCDT1LL [R] 00000000
Remote controller 1
RCCKD1 [R/W] 00000000 00000000 Reserved SCR6 [R, R/W] 0--00000 SMR6 [W, R/W] 000-0000
Reserved
Reserved ESCR6 [R/W] --000000 BGR60 [R/W] 00000000
SSR6 [R, R/W] 0-000011 BGR61 [R/W] 00000000
0001B4H
RDR6/TRD6 [R/W] -------- 00000000 : RDR6 -------- 11111111 : TRD6 ISMK6 [R/W] 01111110 SCR7 [R, R/W] 0--00000 IBSA6 [R/W] 00000000
Serial interface 6
0001B8H 0001BCH 0001C0H
Reserved
Reserved SMR7 [W, R/W] 000-0000 SSR7 [R, R/W] 0-000011 BGR71 [R/W] 00000000 ESCR7 [R/W] --000000 BGR70 [R/W] 00000000
0001C4H
RDR7/TRD7 [R/W] -------- 00000000 : RDR7 -------- 11111111 : TRD7 ISMK7 [R/W] 01111110 IBSA7 [R/W] 00000000
Serial interface 7
0001C8H 0001CCH
Reserved
Reserved (Continued)
37
MB91313 Series
Address 0001D0H
Register 0 SCR8 [R, R/W] 0--00000 1 SMR8 [W, R/W] 000-0000 2 SSR8 [R, R/W] 0-000011 BGR81 [R/W] 00000000 3 ESCR8 [R/W] --000000 BGR80 [R/W] 00000000
Block
0001D4H
RDR8/TRD8 [R/W] -------- 00000000 : RDR8 -------- 11111111 : TRD8 ISMK8 [R/W] 01111110 SCR9 [R, R/W] 0--00000 IBSA8 [R/W] 00000000
Serial interface 8
0001D8H 0001DCH 0001E0H
Reserved
Reserved SMR9 [W, R/W] 000-0000 SSR9 [R, R/W] 0-000011 BGR91 [R/W] 00000000 ESCR9 [R/W] --000000 BGR90 [R/W] 00000000
0001E4H
RDR9/TRD9 [R/W] -------- 00000000 : RDR9 -------- 11111111 : TRD9 ISMK9 [R/W] 01111110 SCRA[R, R/W] 0--00000 IBSA9 [R/W] 00000000
Serial interface 9
0001E8H 0001ECH 0001F0H
Reserved
Reserved SMRA [W, R/W] 000-0000 SSRA [R, R/W] 0-000011 BGRA1 [R/W] 00000000 ESCRA[R/W] --000000 BGRA0 [R/W] 00000000
0001F4H
RDRA/TRDA [R/W] -------- 00000000 : RDRA -------- 11111111 : TRDA ISMKA [R/W] 01111110 IBSAA [R/W] 00000000
Serial interface 10
0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H
Reserved
Reserved DMACA0 [R/W] 00000000 00000000 00000000 00000000 DMACB0 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 00000000 00000000 00000000 DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 00000000 00000000 00000000 DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 00000000 00000000 00000000 DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 00000000 00000000 00000000 (Continued) DMAC
38
MB91313 Series
Address 000224H 000228H to 00023CH 000240H 000244H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H to 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00043CH
Register 0 1 2 3 DMACB4 [R/W] 00000000 00000000 00000000 00000000 Reserved DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX Reserved BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] 00000000 DDR4 [R/W] 00000000 DDRC [R/W] 00000000 DDR1 [R/W] 00000000 DDR5 [R/W] 00000000 DDRD [R/W] 00000000 DDR2 [R/W] 00000000 DDR6 [R/W] --000000 DDRE [R/W] 00000000 DDR3 [R/W] 00000000 Reserved
Block
DMAC
Reserved
Bit search module
Reserved DDRF [R/W] 00000000
Data direction register
Reserved Reserved PFR0 [R/W] 00000000 PFR4 [R/W] 00000000 PFRC [R/W] 00000000 PFR1 [R/W] 00000000 PFR5 [R/W] 00000000 PFRD [R/W] 00000000 PFR2 [R/W] 00000000 PFR6 [R/W] --000000 PFRE [R/W] 00000000 PFR3 [R/W] 00000000 Reserved Port function register PFRF [R/W] 00000000 Reserved
Reserved
Reserved Reserved Reserved (Continued) 39
MB91313 Series
Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH 000490H 000494H to 0004FCH
Register 0 ICR00 [R, R/W] ---11111 ICR04 [R, R/W] ---11111 ICR08 [R, R/W] ---11111 ICR12 [R, R/W] ---11111 ICR16 [R, R/W] ---11111 ICR20 [R, R/W] ---11111 ICR24 [R, R/W] ---11111 ICR28 [R, R/W] ---11111 ICR32 [R, R/W] ---11111 ICR36 [R, R/W] ---11111 ICR40 [R, R/W] ---11111 ICR44 [R, R/W] ---11111 1 ICR01 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 2 ICR02 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 3 ICR03 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 ICR47 [R, R/W] ---11111
Block
Interrupt control unit
Reserved RSRR [R, R/W] 10000000 CLKR [R/W] 00000000 STCR [R/W] 00110011 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00 DIVR0 [R/W] 00000011 OSCCR [R/W] XXXXXXX0 Reserved OSCT [R/W] XXXXXXXX Reserved Reserved CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 Reserved
Reserved
Clock control unit
Reserved WPCR [R/W] 00000000 OSCR [R/W] 00000000
Clock timer Stabilization wait timer Reserved (Continued)
40
MB91313 Series
Address 000500H 000504H 000508H to 000510H 000514H to 00051CH 000520H 000524H 000528H 00052CH 000530H 000534H to 00056CH 000570H 000574H 000578H 00057CH to 00063CH 000640H 000644H 000648H 00064CH 000650H to 00065CH 000660H
Register 0 PCR0 [R/W] 00000000 Reserved 1 PCR1 [R/W] 00000000 PCR5 [R/W] 00000000 2 Reserved PCR6 [R/W] --000000 Reserved 3
Block
Port pull-up control registers
Reserved
Reserved EPFR0 [R/W] 00000000 EPFR4 [R/W] 11111111 EPFRC [R/W] 00000000 EPFR1 [R/W] 00000000 EPFR5 [R/W] 11111111 EPFRD [R/W] 00000000 EPFR2 [R/W] 11111111 EPFR6 [R/W] --001000 EPFRE [R/W] 00000000 EPFR3 [R/W] 11111111 Reserved
Reserved
Reserved EPFRF [R/W] 00000000
External port function register
Reserved Reserved ADER[R/W] 00000011 11111111 Reserved NSF[R/W] -----000 00000000 Reserved ASR0 [R/W] 00000000 00000000 ASR1 [R/W] 00000000 XXXXXXXX ASR2 [R/W] 00000000 XXXXXXXX ASR3 [R/W] 00000000 XXXXXXXX Reserved AWR0 [R/W] 01110000 01011011 AWR1 [R/W] 0XXX0000 0X0X1XXX (Continued) 41 ACR0 [R/W] 00110X00 00000000 ACR1 [R/W] 00XX0X00 00X0XXXX ACR2 [R/W] 00XX0X00 00X0XXXX ACR3 [R/W] 00XX0X00 00X0XXXX Reserved Reserved EXT/I2C/ A/D Reserved I2C Noise filter Reserved
Reserved
External bus interface
MB91313 Series
Address 000664H 000668H to 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH 42
Register 0 1 2 3 AWR2 [R/W] 0XXX0000 0X0X1XXX Reserved CSER[R/W] 00000001 Reserved Reserved MODR [W] XXXXXXXX Reserved AWR3 [R/W] 0XXX0000 0X0X1XXX
Block
External bus interface Reserved
Unused Unused
Reserved
Reserved
Reserved DMASA0 [R/W] 00000000 00000000 00000000 00000000 DMADA0 [R/W] 00000000 00000000 00000000 00000000 DMASA1 [R/W] 00000000 00000000 00000000 00000000 DMADA1 [R/W] 00000000 00000000 00000000 00000000 DMASA2 [R/W] 00000000 00000000 00000000 00000000 DMADA2 [R/W] 00000000 00000000 00000000 00000000 DMASA3 [R/W] 00000000 00000000 00000000 00000000 DMADA3 [R/W] 00000000 00000000 00000000 00000000 DMASA4 [R/W] 00000000 00000000 00000000 00000000 DMADA4 [R/W] 00000000 00000000 00000000 00000000 Reserved
Reserved
DMAC
Reserved
MB91313 Series
(Continued) Address 007000H 007004H Register 0 FLCR[R/W] 0000X000 FLWC[R/W] 00011011 1 2 Reserved Flash I/F Reserved 3 Block
43
MB91313 Series
VECTOR TABLE
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception System reserved External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 RX/I2C status UART0 TX UART1 RX/I C status UART1 TX UART2 RX/I2C status UART2 TX UART3 RX/TX/I C status
2 2
Interrupt number
Decimal Hexadecimal
Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17
Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H
DMAC TBR default DMA STOP transfer source address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21
000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H

STOP STOP STOP
(Continued)
44
MB91313 Series
Interrupt source UART4 RX/TX/I2C status UART5 RX/TX/I2C status UART6 RX/TX/I C status UART7 RX/TX/I C status UART8 RX/TX/I C status UART9 RX/TX/I2C status UART10 RX/TX/I2C status A/D converter PPG0 PWC HDMI-CEC/Remote controller 0, 1 Watch timer Main oscillation wait Timebase timer Reload timer 3 Reload timer 4 Reload timer 5 PPG1 PPG2 PPG3 DMAC0 DMAC1 DMAC2 DMAC3 DMAC4 External interrupt 8 to 15 External interrupt 16 to 23 Multi-function timer 0, 1 Multi-function timer 2, 3 Delay interrupt System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved
2 2 2
Interrupt number
Decimal Hexadecimal
Interrupt level ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H
DMAC TBR default DMA STOP transfer source address
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42
000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H

(Continued) 45
MB91313 Series
(Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number
Decimal Hexadecimal
Interrupt level
Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H
DMAC TBR default DMA STOP transfer source address
67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H

46
MB91313 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Analog power supply voltage*1 Input voltage*1 Analog pin input voltage* Output voltage*
1 1
Symbol VDDE (3.3 V) VDDI (1.8 V) AVCC AVRH VI VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD Tstg
Rating Min Vss - 0.5 Vss - 0.3 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 - 40 Max Vss + 4.0 Vss + 2.5 Vss + 4.0 Vss + 4.0 VDDE + 0.5 Vss + 6.0 AVcc + 0.5 VDDE + 0.5 8 4 60 30 -8 -4 - 60 - 30 300 + 125
Unit V V V V V V V V mA mA mA mA mA mA mA mA mW C
Remarks
5 V tolerant pin
"L" level maximum output current*2 "L" level average output current*3 "L" level total maximum output current "L" level total average output current*4 "H" level maximum output current*2 "H" level average output current*3 "H" level total maximum output current "H" level total average output current*4 Power consumption Storage temperature
*1 : This parameter is based on VSS = AVSS = 0.0 V *2 : The maximum output current is the peak value for a single pin. *3 : The average output current is the average current for a single pin over a period of 100 ms. *4 : The total average output current is the average current for all pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
47
MB91313 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Operating temperature Power supply voltage Analog power supply voltage 5 V tolerant pin input voltage Symbol Ta VDDE (3.3 V) VDDI (1.8 V) AVCC VI Value Min - 40 3.0 1.65 3.0 Max + 85 3.6 1.95 VDDE VSS + 5.5 Unit C V V V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
48
MB91313 Series
3. DC Characteristics
(VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 40 C to + 85 C) Parameter Symbol Pin name ICCT ICC ICCS ICCL ICCH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1, PF0 to PF7 PE2 to PE7, PC0 to PC7, P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1, PF0 to PF7 PE2 to PE7, PC0 to PC7, P40 to P47 "H" level output voltage "L" level output voltage VOH VOL All port pins All port pins VDDE = 3.3 V, IOH = - 4 mA VDDE = 3.3 V, IOL = 4 mA Conditions Clock mode Ta = + 25 C, fclk = 32 kHz During normal operation Ta = + 25 C, fcp = 33 MHz, fcpp = 33 MHz Main sleep mode Ta = + 25 C, fcp = 33 MHz, fcpp = 33 MHz Sub RUN mode Ta = + 25 C, fclk = 32 kHz Main Stop mode Ta = + 25 C, fclk = 0 Main Stop mode Ta = + 70 C, fclk = 0 Value Min Typ 200 100 55 25 30 15 250 150 150 40 400 100 Max 400 300 80 40 50 30 450 400 300 80 800 200 A A A mA mA A Unit
Current Consumption (upper : 1.8 V lower : 3.3 V)
"H" level input voltage
VDDE x 0.8 VDDE = 3.3 V VDDE x 0.7
VDDE
V
VIH
VDDE
V
"L" level input voltage
VSS VDDE = 3.3 V VSS VDDE - 0.5 VSS
VDDE x 0.2
V
VIL

VDDE x 0.3 VDDE 0.4
V V V
(Continued)
49
MB91313 Series
(Continued) (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 40 C to + 85 C) Symbol Pin name Other than PD0 to PD7, PE0, PE1 PD0 to PD7, PE0, PE1 Pull-up : P00 to P07, P10 to P17, P50 to P57, P60 to P65, INITX, TRSTX Pull-down : ICD0 to ICD3, IBREAK Between P21 and P24 Between P22 and P25 Between P24 and P27 Between P25 and P30 Pull-up : VIL = 0 V Pull-down : VIH = VDDE Conditions Value Min -5 - 10 Typ Max +5 + 10 Unit A A
Parameter
Input leak current
IIL
Pull-up/ Pull-down resistance
RP
10
33
80
k
I2C bus switch connection resistance
RBS
130
50
MB91313 Series
4. AC Characteristics
(1) Clock Timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks
Clock frequency
fC
X0, X1
10
16.5
33
PLL clock (self-oscillation 16.5 MHz doubled via MHz PLL : internal operation at 33 MHz max.) kHz MHz CPU MHz Peripheral MHz External bus
Sub clock frequency Internal operating clock frequency
fclk fCP fCPP fCPT
X0A, X1A

32.768
33 33 16.5

(2) Clock Output Timing (VDDE = AVCC = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = AVSS = 0 V, Ta = - 40 C to + 85 C) Parameter Cycle time CLK CLK CLK CLK Symbol tCYC tCHCL tCLCH Pin name CLK CLK CLK Conditions Value Min 60.7 1/2 x tCYC - 5 1/2 x tCYC - 5 Max 1/2 x tCYC + 5 1/2 x tCYC + 5 Unit Remarks ns ns ns *1 *2 *3
*1 : tCYC is the frequency of one clock cycle after gearing. *2 : These ratings are for the gear ratio set to x 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. (1/2 x 1/n) x tCYC - 10 *3 : These ratings are for the gear ratio set to x 1.
tCYC tCHCL VOH tCLCH VOH
CLK
VOL
(3) PLL Oscillation Stabilization Wait Time (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 40 C to + 85 C) Parameter PLL oscillation stabilization wait time Symbol tLOCK Value Min 600 Max Unit s Remarks The length of time to wait for the PLL oscillations to stabilize. 51
MB91313 Series
(4) Reset Input (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = - 40 C to + 85 C) Parameter INITX input time (at power-on) INITX input time (other than power-on) INITX input time (Stop recovery time) tINTL INITX Symbol Pin name Conditions Value Min Oscillation stabilization delay time of oscillator + tcp x 10 tcp x 10 Oscillation stabilization delay time of oscillator + tcp x 10 Max Unit s ns s
tINTL
INITX
0.2 VCC
52
MB91313 Series
(5) Normal Access Read/Write Operation (VDDE = AVCC = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = AVSS = 0 V, Ta = - 40 C to + 85 C) Parameter Symbol tCSLCH CS0X to CS3X setup tCSDLCH CS0X to CS3X hold Address setup time Address hold time WR0X, WR1X delay time WR0X, WR1X delay time WR0X, WR1X minimum pulse width Data setup WRxX WRxX Data hold time RDX delay time RDX delay time RDX Valid data input time Data setup RDX Time RDX Data hold time RDX minimum pulse width ASX setup ASX hold tCHCSH tASCH tCHAX tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tASHCH RDX CLK ASX RDX AD15 to AD00 CLK AD15 to AD00 CLK WR0X, WR1X WR0X, WR1X WR0X, WR1X AD15 to AD00 CLK RDX CLK CS0X to CS3X Pin name Conditions AWRxL : WO2 = 0 AWRxL : WO2 = 1 Value Min 3 -3 3 3 3 12 tCYC 3 30 0 12 3 3 Max 1/2 x tCYC + 6 1/2 x tCYC + 6 6 6 6 6 tCYC - 30 1/2 x tCYC + 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *2 Remarks *1 *1
*1 : AWRxL : Area Wait Register *2 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC x the number of cycles added for the delay) to this rating.
53
MB91313 Series
(6) Multiplexed Bus Access Read/Write Operation (VDDE = 3.3 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter AD15 to AD00 address setup time CLK CLK AD15 to AD00 address setup time AD15 to AD00 address setup time ASX ASX AD15 to AD00 address setup time Symbol tASCH tCHAX tASASH tASHAX Pin name Conditions Value Min 3 3 ASX AD15 to AD00 12 tCYC - 3 tCYC + 3 ns ns * * Max 1/2 x tCYC + 6 Unit Remarks ns ns
CLK AD15 to AD00
* : CSxX RDX/WRxX setup extension = 1 Note : Use the same rating as normal bus interface except for this rating.
54
MB91313 Series
* CSxX RDX/WRxX setup extension = 1
tCYC BA1 BA1W BA2 BA3
CLK
tASLCH
tASHCH
ASX
tASASH tCSLCH
tASHAX
CS0X to CS3X
tASCH tCHAX
AD15 to AD00
Address
Read data
tDSRH tRLDV
tRHDX
RDX
tRLRH tCHRL tCHRH
AD15 to AD00
Address
Write data
tDSWH tWHDX
WR0X, WR1X
tWLWH tCHWL tCHWH
55
MB91313 Series
* CSxX RDX/WRxX setup extension = 0
tCYC BA1 BA2 BA3
CLK
ASX
tASLCH
tASHCH
tCSLCH
CS0X to CS3X
tASCH tCHAX
AD15 to AD00
Address
Read data
tDSRH tRLDV
tRHDX
RDX
tRLRH tCHRL tCHRH
AD15 to AD00
Address
Write data
tDSWH
tWHDX
WR0X, WR1X
tWLWH tCHWL tCHWH
56
MB91313 Series
(7) Ready Input Timings (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter RDY setup time CLK CLK RDY hold time Symbol tRDYS tRDYH Pin name CLK, RDY CLK, RDY Conditions Value Min 25 0 Max Unit ns ns
tCYC
CLK
VOL
VOH VOL
VOH
tRDYS tRDYH
tRDYS tRDYH
RDY wait applied
VOH VOL VOL
VOH
RDY wait not applied
VOH VOL
VOH VOL
57
MB91313 Series
(8) UART timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK10 SCK0 to SCK10 SOT0 to SOT10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SCK0 to SCK10 SCK0 to SCK10 SOT0 to SOT10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SIN0 to SIN10 External shift clock operation Conditions Value Min 4 tCYCP - 20 Internal shift clock operation 30 20 2 tCYCP 2 tCYCP 20 20 Max + 20 30 Unit ns ns ns ns ns ns ns ns ns
Notes : * The above standards apply to the CLK synchronous mode. * tCYCP indicates the peripheral clock cycle time.
58
MB91313 Series
* Internal shift clock mode
tSCYC
SCK0 to SCK10
VOL tSLOV
VOH
VOL
SOT0 to SOT10
VOH VOL tIVSH tSHIX VOH VOL
SIN0 to SIN10
VOH VOL
* External shift clock mode
tSLSH tSHSL VOH VOH
SCK0 to SCK10
VOL tSLOV
VOL
SOT0 to SOT10
VOH VOL tIVSH tSHIX VOH VOL
SIN0 to SIN10
VOH VOL
59
MB91313 Series
(9) Reload timer clock, PPG timer input, multi-function timer input timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0 to TIN5 TRG0 to TRG3 Conditions Value Min 2 tCYCP Max Unit ns
Note : tCYCP is the cycle time of the peripheral clock.
TIN0 to TIN5 TRG0 to TRG3
tTIWH tTIWL
(10) Trigger Input Timing (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter A/D activation trigger input time Symbol tATRG Pin name ATRG Conditions Value Min 5 tCYCP Max Unit ns
Note : tCYCP is the cycle time of the peripheral clock.
tATRG
ATRG
60
MB91313 Series
(11) Remote control signal input timing (VDDE = 3.3 V + 0.3 V, VDDI = 1.8 V + 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter
Remote control input pulse width
Symbol Pin name tRCIN RCIN0 RCIN1
Conditions At 32.768 kHz
Value Min 62 Max
Unit s
Parameter
Count 2 clocks or more
tRCIN
RCIN0 RCIN1
61
MB91313 Series
(12) I2C timing * When operating in master mode (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock Bus free time between "STOP condition" and "START condition" SCL SDA output delay time "Repeated START condition" setup time SCL SDA "Repeated START condition" hold time SDA SCL "STOP condition" setup time SCL SDA SDA data input hold time (vs. SCL ) SDA data input setup time (vs. SCL ) Symbol Conditions fSCL tLOW tHIGH tBUS Typical mode Min 0 4.7 4.0 4.7 R = 1 k, C = 50 pF*2 4.7 Max 100 5 x M*3 High-speed mode*1 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*3 kHz s s s ns s s s s ns The first clock pulse is generated after this. Unit Remarks
tDLDAT tSUSTA
tHDSTA
4.0
0.6
tSUSTO tHDDAT tSUDAT
4.0 2 x M*3 250
0.6 2 x M*3 100*4
*1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher. *2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. *3 : M = Resource clock cycle (ns) *4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". When a device does not extend the "L" period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) from when the SCL line is released.
62
MB91313 Series
* When operating in slave mode (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock Bus free time between "STOP condition" and "START condition" SCL SDA output delay time "Repeated START condition" setup time SCL SDA "Repeated START condition" hold time SDA SCL "STOP condition" setup time SCL SDA SDA data input hold time (vs. SCL ) SDA data input setup time (vs. SCL) Symbol Conditions fSCL tLOW tHIGH tBUS Typical mode Min 0 4.7 4.0 4.7 R = 1 k, C = 50 pF*2 4.7 Max 100 5 x M*3 High-speed mode*1 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*3 kHz s s s ns s s s s ns The first clock pulse is generated after this. Unit Remarks
tDLDAT tSUSTA
tHDSTA
4.0
0.6
tSUSTO tHDDAT tSUDAT
4.0 2 x M*3 250
0.6 2 x M*3 100*4
*1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher. *2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. *3 : M = Resource clock cycle (ns) *4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". When a device does not extend the "L" period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) from when the SCL line is released.
63
MB91313 Series
5. Electrical Characteristics for the A/D Converter
(1) Electrical Characteristics (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, Ta = -40 C to + 85 C) Parameter Resolution Total error*1 Nonlinear error*1 Differential linear error*1 Zero transition voltage*1 Full transition voltage*1 Conversion time Power supply current (analog + digital) Reference power supply current (between AVRH and AVSS) Analog input capacitance Interchannel disparity *1 : Measured in the CPU sleep state *2 : Depending on the clock cycle supplied to peripheral resources Value Min - 4.0 AVRH - 5.5 7.94*2 Typ Max 10 5.5 3.5 2.0 + 6.0 AVRH + 3.0 3 100 21 4 Unit bit LSB LSB LSB LSB LSB s mA A pF LSB AVRH = 3.0 V, AVSS = 0.0 V AVcc = 3.3 V, AVRH = 3.3 V (CPU sleep) Remarks
RIN
Comparator
AN9 to AN0 Analog input pin
CIN
RIN = 5 k CIN = 21 pF
64
MB91313 Series
* The relationship between peripheral clock and external impedance (Peripheral clock frequency and external impedance)
MB91F313
120 110 100 90 80 70 60 50 40 30 20 20 15 20 25 30 35 40 120 110 100 90 80 70 60 50 40 30 20 10
(Peripheral clock cycle and external impedance)
MB91F313
External impedance [k]
External impedance [k]
30
50
70
90
110
Peripheral clock frequency [MHz]
Peripheral clock cycle [ns]
65
MB91313 Series
(2) Definition of terms : Analog variation that is recognized by an A/D converter. : The deviation between the actual conversion characteristics and a straight line connecting the device's zero transition point ("00 0000 0000B" "00 0000 0001B") and full scale transition point ("11 1111 1110B" "11 1111 1111B"). Differential linear error : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Total error : This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error Resolution Linearity error
Linearity error
3FFH 3FEH {1 LSB' (N - 1) + VOT} 3FDH
Actual conversion characteristics
Differential linearity error
Actual conversion characteristics
(N + 1)H
Digital output
Digital output
VFST (measurement value) 004H 003H 002H 001H VNT (measurement value)
Actual conversion characteristics Ideal characteristics
Ideal characteristics
NH
(N - 1)H
V(N + 1)T (measurement value) VNT (measurement value) Actual conversion characteristics AVRH
(N - 2)H
VOT (measurement value) AVRH AVSS
AVSS
Analog input
Analog input
VNT - {1 LSB' x (N - 1) + VOT} [LSB] 1 LSB' V (N+1) T - VNT Differential linear error in digital output N = -1[LSB] 1 LSB' VFST - VOT 1 LSB = [V] 1022 Linear error in digital output N = N VOT VFST VNT : A/D converter digital output value : The voltage at which digital output changes from (000) H to (001) H : The voltage at which digital output changes from (3FE) H to (3FF) H : The voltage at which digital output changes from (N + 1) H to NH (Continued)
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MB91313 Series
(Continued) Total error
3FFH 3FEH 3FDH 1.5 LSB'
Actual conversion characteristics
{1 LSB' (N - 1) + 0.5 LSB'}
Digital output
004H 003H 002H 001H 0.5 LSB' AVSS
(measurement value)
VNT
Actual conversion characteristics
Ideal characteristics
AVRH
Analog input
1LSB' (ideal value) =
AVRH - AVSS [V] 1024 VNT - {1 LSB' x (N - 1) + 0.5 LSB'} Total error of digital output N = 1 LSB'
N : A/D converter digital output value VNT : The voltage at which digital output changes from (N + 1) H to NH VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V]
67
MB91313 Series
6. Flash Memory Write/Erase Characteristics
(VDDE = 3.3 V, VDDI = 1.8 V, Ta = + 25 C) Parameter Sector erase time Word write time Chip write time Erase/write cycle Data retention time Value Min 10000 20* Typ 0.9 23 6.2 Max 3.6 370 102 Unit s s s cycle year
Average Ta = + 85 C
Remarks Excludes internal programming prior erasure. Excludes system-level overhead. Excludes system-level overhead.
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C).
68
MB91313 Series
ORDERING INFORMATION
Part number MB91F313PMC-GE1 Package 120-pin plastic LQFP (FPT-120P-M21)
69
MB91313 Series
PACKAGE DIMENSION
120-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 16.0 x 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88 g P-LFQFP120-16x16-0.50
(FPT-120P-M21)
Code (Reference)
120-pin plastic LQFP (FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
18.000.20(.709.008)SQ
* 16.00 -0.10 .630 +.016 SQ -.004
90 61
+0.40
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX 0~8
120 31
"A" 0.100.05 (.004.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 .006
+0.05 -0.03 +.002 -.001
0.600.15 (.024.006)
C
2002 FUJITSU LIMITED F120033S-c-4-4
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
70
MB91313 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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